Digital delay interpolation is a method for performing a fine delay with a better resolution. FIG. 1 shows a prior art digital delay interpolator, disclosed in the U.S. Published Patent Application No. 2003/0006817. This delay interpolator comprises a plurality of delay stages to control delay time of an output signal from two input signals having different phase delays. The digital delay interpolator includes four delay stages (100-110-120-130) that have the same internal structure. The first delay stage 100 includes inverters 510, 520, 530, 540, a phase mixer 550, and a multiplexer 3×2 560. The input signals IN1 and IN2 are inverted by inverters 510, 520 that provide the inverted replicas thereof to the phase mixer 550. The phase mixer 550 includes inverters 552, 554 having outputs connected to each other, and generates the first phase mixing signal PB1 (see FIG. 2) having an intermediate phase between the signals IN1D and IN2D. The signals IN1D and IN2D are inverted by the inverters 530, 540 and the multiplexer 560 generates the output signals OUT1 and OUT2 by selecting one of signals outputted by the inverters 530, 540, and the phase mixed signal PB1. The delay stages 110, 120 and 130 are identical to the first delay stage 100.
With this architecture, the signal outputted from the fourth stage 130 has a delay resolution equal to Δ/16, wherein Δ is the delay between the input signals IN1 and IN2 of the first stage 100. In order to obtain a resolution equal to Δ/2K, K stages in cascade are necessary. Therefore, the accuracy of this delay interpolator may be enhanced only by increasing the number of stages in cascade, that may cause relatively long propagation delays along the whole structure and a large power consumption.